Receiver circuits for sampling a received data waveform and in particular ones which include circuitry for setting the sampling point when jitter is present in the received waveform are known. Traditionally an analogue phase locked loop (PLL) circuit was used to control a local clock signal which is used to time the data samples, with the frequency of the local oscillator that is the source of that local clock signal being controlled by the feedback loop. In more modern implementations a fixed frequency oscillator is used and the fixed clock signal that it produces is passed through a phase interpolator to select dynamically an appropriate phase for the local clock signal that is then used to time the data sample. (A phase interpolator that may be used for clock recovery is described in GB patent 2 362 045.) In either case, in order to control the timing of the local clock signal, the circuit detects the difference in between phase of the local clock signal and phase of the data waveform. Numerous methods for detecting this phase difference are known in the art. One such arrangement which provides a SERDES application is described in GB patent Application 2 446 513.
A figure of merit for these receiver circuits is the bit error rate (BER) which is detected by transmitting to the receiver circuit a known pattern of data and then checking each bit to see if it is correct.
In the prior art for the purpose of such evaluation a more advanced method of a fixed static phase offset has been applied to the data sample position, which increases the data error rate since the sampling position is not ideal, but this method requires suspension of some aspect of the control loop, or if the application is to continue, significant duplication of the critical components.